Explore with PCBMASTER --- In high - speed PCB design, how to address the eye diagram collapse of signals above 10Gbps

Author: Jack Wang

1. The Golden Rules of Stack - Up Design

① Material Selection

When the signal rate is ≥10Gbps, ultra - low - loss materials (such as Megtron6 with Df = 0.002) should be preferred. In a certain optical module case, after replacing FR - 4, the insertion loss was reduced by 40% (@28GHz).

② Stack - Up Symmetry

2. Three Fatal Details in Differential Pair Routing

① Length Matching

A length difference of 1000mil introduces a 1ps delay deviation. For 56G PAM4 signals, the total deviation should be <0.5ps. When using serpentine traces, the amplitude should be ≥5 times the line width, and the spacing should be ≥3 times the line width.

② Reference Layer Break

In a certain server motherboard, the impedance mutation caused by the power layer division deteriorated the S - parameter by 8dB at 12GHz. Solution: Add a 0.1μF capacitor array on both sides of the divided area to form a high - frequency return path.

③ Via Optimization

For signals above 12Gbps, the back - drill process is required, and the remaining stub length should be ≤1/10 of the signal wavelength. For example, for a 28GHz signal, the stub should be <7mil.

3. Tips for Measurement and Verification

Eye Diagram Test

The de - embedding function must be enabled to eliminate the influence of the test fixture. In an FPGA verification case, the measured jitter was 12ps without de - embedding, while the true value was only 6.8ps.

TDR Impedance Analysis

The sampling point density should be ≥5 points/mm, and the accuracy of locating impedance mutation points can reach ±0.5mm.

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Author: Jack Wang